preliminary 512k x 24 static ram module cym8301v33 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05092 rev. ** revised july 5, 2001 01 features high density 12- mb sram module high speed cmos srams access times of 10 ns single 3.3v power supply low active power(1620w at 10 ns) ttl compatible inputs and outputs available in standard 119 ball bga interface to motorola dsp and analog devices functional description the cym8301 is a 3.3v high performance 12 megabit static ram organized as a 512k words by 24 bits. this module is constructed from three 512k x8 sram dies mounted on a multi layer laminate substrate combined to form a 24 bit sram. cym8301 is an ideal single chip solution for the mo- torola ? s dsp5630x or a two chip solution to analog devices adsp2106xl. each data byte is separately controlled by the individual chip selects(ce 0 /,ce 1 /ce 2 /). ce0/ controls i/o 0-7 . ce 1 / controls i/o 8-15 . ce 2 / controls i/o 16-23 . writing the data bytes into the sram is accomplished when the chip select controlling that byte is low and write enable (we ) input is low. data on the respective input/output pins (i/o) is then written into the memory location specified on the address pins (a 0 through a 18 ). asserting all the chip selects low and write enable low will write the entire da- ta(i/o 0 -i/o 23 ) into the sram. output enable (oe ) is not looked into while in a write mode. data bytes can also be individually read from the device. reading a byte is accomplished when the chip select control- ling that byte is low and write enable (we ) high while ouput enable (oe ) remains low. under these conditions, the con- tents of the memory location specified on the address pins will appear on the specified data input/output pins (i/o). asserting all the chip selects low and write enable high with output enable low will read the entire data (i/o 0 -i/o 23 ) from the sram. the data input/output (i/o0-i/o23) pins stay at high-imped- ance state when all the chip selects are high or when the output enable (oe ) is high when in a read mode. for further details, refer to the truth table in this datasheet. functional block diagram a[18:0] we/ oe/ ce0/ ce1/ ce2/ i/o 0-23 i/o 0-7 i/o 8-15 i/o 16-23 i/o 0-7 i/o 8-15 i/o 16-23 ce0/ a[18:0] a[18:0] a[18:0] ce1/ ce2/ we/ oe/ oe/ oe/ we/ we/ 8 8 8 24
cym8301v33 preliminary document #: 38-05092 rev. ** page 2 of 9 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c supply voltage on v cc to relative gnd [1] ...... ? 0.5v to 4.6v dc voltage applied to outputs in high z state [1] ................................... ? 0.5v to v cc + 0.5v dc input voltage [1] ............................... ? 0.5v to v cc + 0.5v current into outputs (low) ........................................ 20 ma static discharge voltage ........................................... >2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma notes: 1. v il (min.) = ? 2.0v for pulse durations of less than 20 ns. 2. t a is the ? instant on ? case temperature. selection guide cym8301-10 cym8301-12 cym8301-15 maximum access time (ns) 10 12 15 maximum operating current (ma) 450 420 420 maximum standby current (ma) 90 90 90 shaded areas contain advance information. pin configurations 119 bga top view 1234567 a ncaaaaanc b nc a a ce0 aanc c i/o 12 nc ce1 nc ce2 nc i/0 0 d i/o 13 v dd v ss v ss v ss v dd i/o 1 e i/o 14 v ss v dd v ss v dd v ss i/o 2 f i/o 15 v dd v ss v ss v ss v dd i/o 3 g i/o 16 v ss v dd v ss v dd v ss i/o 4 h i/o 17 v dd v ss v ss v ss v dd i/o 5 j nc v ss v dd v ss v dd v ss nc k 1/o 18 v dd v ss v ss v ss v dd i/o 6 l i/o 19 v ss v dd v ss v dd v ss i/o 7 m i/o 20 v dd v ss v ss v ss v dd i/o 8 n i/o 21 v ss v dd v ss v dd v ss i/o 9 p i/o 22 v dd v ss v ss v ss v dd i/o 10 r i/o 23 a ncncnc ai/o 11 t nc a a we aanc u nc a a oe aanc operating range range ambient temperature [2] v cc commercial 0 c to +70 c 3.3v 5% industrial ? 40 c to +85 c 3.3v 5% shaded areas contain advance information.
cym8301v33 preliminary document #: 38-05092 rev. ** page 3 of 9 electrical characteristics over the operating range parameter description test conditions [3] cym8301-10 cym8301-12/15 min. max. min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage [1] ? 0.5 0.8 ? 0.5 0.8 v i ix input load current gnd < v i < v cc ? 10 +10 ? 10 +10 a i oz output leakage current gnd < v i < v cc , output disabled ? 10 +10 ? 10 +10 a i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 450 420 ma i sb1 automatic ce power-down current ? ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 150 150 ma i sb2 automatic ce power-down current ? cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 90 90 ma capacitance [4] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 8pf c out output capacitance 8 pf ac test loads and waveforms notes: 3. ce is a combination of ce1 , ce2 and ce3 4. tested initially and after any design or process changes that may affect these parameters. 1024v33 ? 3 1024v33 ? 4 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 5 pf including jig and scope (a) (b) 3 ns 3ns r1 317 ? r2 351 ? output r l =50 ? z 0 =50 ? v th = 1.5v
cym8301v33 preliminary document #: 38-05092 rev. ** page 4 of 9 switching characteristics [5] over the operating range cym8301-10 cym8301-12 cym8301-15 parameter description [3] min. max. min. max. min. max. unit read cycle t rc read cycle time 10 12 15 ns t aa address to data valid 10 12 15 ns t oha data hold from address change 3 33ns t ace ce active to data valid 10 12 15 ns t doe oe low to data valid 67.28.5ns t lzoe oe low to low z 0 00ns t hzoe oe high to high z [6, 7] 567ns t lzce ce active to low z [7] 3 33ns t hzce ce inactive to high z [6, 7] 567ns t pu ce active to power-up 0 00ns t pd ce inactive to power-down 10 12 15 ns write cycle [8, 9] t wc write cycle time 10 12 15 ns t sce ce active to write end 9 99ns t aw address set-up to write end 9 910ns t ha address hold from write end 0 00ns t sa address set-up to write start 0 00ns t pwe we pulse width 8 10 11 ns t sd data set-up to write end 6 67ns t hd data hold from write end 0 00ns t lzwe we high to low z [7] 3 33ns t hzwe we low to high z [6, 7] 567ns notes: 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh . 6. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 7. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 8. the internal write time of the memory is defined by the overlap of ce low and we low. ce and we must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd .
cym8301v33 preliminary document #: 38-05092 rev. ** page 5 of 9 switching waveforms read cycle no. 1 [10, 11] read cycle no. 2 (oe controlled) [3, 11, 12] write cycle no. 1 (ce controlled) [3, 13, 14] notes: 10. device is continuously selected. oe , ce = v il . 11. we is high for read cycle. 12. address valid prior to or coincident with ce transition low. 13. data i/o is high impedance if oe = v ih . 14. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. previous data valid data valid t rc t aa t oha 8301v33 address data out 8301v33 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data out v cc supply current t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce address we data i/o 8301v33
cym8301v33 preliminary document #: 38-05092 rev. ** page 6 of 9 write cycle no. 2 (we controlled, oe high during write) [13, 14] write cycle no. 3 (we controlled, oe low) [3, 14] note: 15. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) 8301v33 t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 15 8301v33 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 15
cym8301v33 preliminary document #: 38-05092 rev. ** page 7 of 9 truth table ce1 ce2 ce3 we oe i/o 0 ?i/o 23 mode h h h x x high z deselect/power down l l l h l data out (i/o 0 - 23 ) read l l l h h i/o high z power down l h h h l data out (i/o 0 -7 ) i/o 8-23 in high z read h l h h l data out (i/o 8- 15 ) i/o 0 -7 in high z i/o 16- 23 in high z read h h l h l data out (i/o 16-23 ) i/o 0 -15 in high z read l l l l x data in (i/o 0 -23 ) write l h h l x data in (i/o 0-7 ) write h l h l x data in (i/o 8 - 15 ) write h h l l x data in (i/o 16- 23 ) write ordering information speed (ns) ordering code package name package type operating range 10 cym8301v33 - 10 bgc bg119 119-ball bga commercial 12 cym8301v33 - 12 bgc bg119 119-ball bga commercial 15 cym8301v33 - 15 bgc bg119 119-ball bga commercial 15 cym8301v33 - 15 bgi bg119 119-ball bga industrial
cym8301v33 preliminary document #: 38-05092 rev. ** page 8 of 9 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram 119-ball bga (14 x 22 x 2.4 mm) bg119 51-85115
cym8301v33 preliminary document #: 38-05092 rev. ** page 9 of 9 document title: cym8301v33 512 x 24 static ram module document number: 38-05092 rev. ecn no. issue date orig. of change description of change ** 107602 07/17/01 meg new data sheet
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